Dr. Nihar Mohanty Profile

Dr. Nihar Mohanty

R&D Manager at Meta

SPIE Involvement:

Conference Chair | Conference Program Committee | Editor | Author

Proceedings Article | 16 November 2022 Presentation

Challenges and opportunities for near-eye displays in AR/VR

Nihar Mohanty

Proceedings Volume PC12293, PC122930B (2022) https://doi.org/10.1117/12.2644549

KEYWORDS: Augmented reality, Field emission displays, Eye, Virtual reality, Photomasks, Glasses, Sensors, Sensor technology, Semiconductors, Photons

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Proceedings Article | 13 June 2022 Presentation

Materials development for immersive augmented reality experiences

Ankit Vora, Nihar Mohanty, Keren Zhang, Giuseppe Calafiore, Tingling Rao, Heeyoon Lee, Geraud Dubois, Matthew Colburn

Proceedings Volume PC12055, PC1205506 (2022) https://doi.org/10.1117/12.2622524

KEYWORDS: Augmented reality, Glasses, Head-mounted displays, Refractive index, Optical lithography, Optical components, Nano optics, Head

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Proceedings Article | 22 February 2021 Presentation

Welcome and Introduction to SPIE Conference 11615

Julie Bannister, Nihar Mohanty

Proceedings Volume 11615, 1161502 (2021) https://doi.org/10.1117/12.2592876

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Proceedings Article | 9 May 2017 Paper

Roughness and uniformity improvements on self-aligned quadruple patterning technique for 10nm node and beyond by wafer stress engineering

Eric Liu, Akiteru Ko, David O'Meara, Nihar Mohanty, Elliott Franke, Karthik Pillai, Peter Biolsi

Proceedings Volume 10149, 101490W (2017) https://doi.org/10.1117/12.2258097

KEYWORDS: Semiconducting wafers, Optical lithography, Plasma etching, Line width roughness, Etching, Silicon, Line edge roughness, Silicon films, Oxides, Lithography

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Dimension shrinkage has been a major driving force in the development of integrated circuit processing over a number of decades. The Self-Aligned Quadruple Patterning (SAQP) technique is widely adapted for sub-10nm node in order to achieve the desired feature dimensions. This technique provides theoretical feasibility of multiple pitch-halving from 193nm immersion lithography by using various pattern transferring steps. The major concept of this approach is to a create spacer defined self-aligned pattern by using single lithography print. By repeating the process steps, double, quadruple, or octuple are possible to be achieved theoretically. In these small architectures, line roughness control becomes extremely important since it may contribute to a significant portion of process and device performance variations. In addition, the complexity of SAQP in terms of processing flow makes the roughness improvement indirective and ineffective. It is necessary to discover a new approach in order to improve the roughness in the current SAQP technique.

In this presentation, we demonstrate a novel method to improve line roughness performances on 30nm pitch SAQP flow. We discover that the line roughness performance is strongly related to stress management. By selecting different stress level of film to be deposited onto the substrate, we can manipulate the roughness performance in line and space patterns. In addition, the impact of curvature change by applied film stress to SAQP line roughness performance is also studied. No significant correlation is found between wafer curvature and line roughness performance. We will discuss in details the step-by-step physical performances for each processing step in terms of critical dimension (CD)/ critical dimension uniformity (CDU)/line width roughness (LWR)/line edge roughness (LER). Finally, we summarize the process needed to reach the full wafer performance targets of LWR/LER in 1.07nm/1.13nm on 30nm pitch line and space pattern.

Proceedings Article | 27 April 2017 Presentation

Dry-plasma-free chemical etch technique for variability reduction in multi-patterning (Conference Presentation)

Subhadeep Kal, Nihar Mohanty, Richard Farrell, Elliott Franke, Angelique Raley, Sophie Thibaut, Cheryl Pereira, Karthik Pillai, Akiteru Ko, Aelan Mosden, Peter Biolsi

Proceedings Volume 10149, 101490P (2017) https://doi.org/10.1117/12.2257507

KEYWORDS: Etching, Plasma, Plasma etching, Optical lithography, Wet etching, Back end of line, Front end of line, Line edge roughness, Chemistry, Line width roughness

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Scaling beyond the 7nm technology node demands significant control over the variability down to a few angstroms, in order to achieve reasonable yield. For example, to meet the current scaling targets it is highly desirable to achieve sub 30nm pitch line/space features at back-end of the line (BEOL) or front end of line (FEOL); uniform and precise contact/hole patterning at middle of line (MOL). One of the quintessential requirements for such precise and possibly self-aligned patterning strategies is superior etch selectivity between the target films while other masks/films are exposed. The need to achieve high etch selectivity becomes more evident for unit process development at MOL and BEOL, as a result of low density films choices (compared to FEOL film choices) due to lower temperature budget. Low etch selectivity with conventional plasma and wet chemical etch techniques, causes significant gouging (un-intended etching of etch stop layer, as shown in Fig 1), high line edge roughness (LER)/line width roughness (LWR), non-uniformity, etc. In certain circumstances this may lead to added downstream process stochastics. Furthermore, conventional plasma etches may also have the added disadvantage of plasma VUV damage and corner rounding (Fig. 1). Finally, the above mentioned factors can potentially compromise edge placement error (EPE) and/or yield.

Therefore a process flow enabled with extremely high selective etches inherent to film properties and/or etch chemistries is a significant advantage. To improve this etch selectivity for certain etch steps during a process flow, we have to implement alternate highly selective, plasma free techniques in conjunction with conventional plasma etches (Fig 2.). In this article, we will present our plasma free, chemical gas phase etch technique using chemistries that have high selectivity towards a spectrum of films owing to the reaction mechanism ( as shown Fig 1). Gas phase etches also help eliminate plasma damage to the features during the etch process. Herein we will also demonstrate a test case on how a combination or plasma assisted and plasma free etch techniques has the potential to improve process performance of a 193nm immersion based self aligned quandruple patterning (SAQP) for BEOL compliant films (an example shown in Fig 2). In addition, we will also present on the application of gas etches for (1) profile improvement, (2) selective mandrel pull (3) critical dimension trim of mandrels, with an analysis of advantages over conventional techniques in terms of LER and EPE.

Proceedings Article | 26 April 2017 Presentation + Paper

EPE improvement thru self-alignment via multi-color material integration

Nihar Mohanty, Jeffrey Smith, Lior Huli, Cheryl Pereira, Angelique Raley, Subhadeep Kal, Carlos Fonseca, Xinghua Sun, Ryan Burns, Richard Farrell, David Hetzer, Andrew Metz, Akiteru Ko, Steven Scheer, Peter Biolsi, Anton DeVillers

Proceedings Volume 10147, 1014704 (2017) https://doi.org/10.1117/12.2258108

KEYWORDS: Optical lithography, Front end of line, Back end of line, Etching, Control systems, Semiconducting wafers, Logic, Extreme ultraviolet, TCAD, Computer simulations, Photomasks, Lithography, Metals

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As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line.

In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.

Proceedings Article | 7 April 2017 Presentation + Paper

Self-aligned block technology: a step toward further scaling

Frédéric Lazzarino, Nihar Mohanty, Yannick Feurprier, Lior Huli, Vinh Luong, Marc Demand, Stefan Decoster, Victor Vega Gonzalez, Julien Ryckaert, Ryan Ryoung Han Kim, Arindam Mallik, Philippe Leray, Chris Wilson, Jürgen Boemmels, Kaushik Kumar, Kathleen Nafus, Anton deVilliers, Jeffrey Smith, Carlos Fonseca, Julie Bannister, Steven Scheer, Zsolt Tokei, Daniele Piumi, Kathy Barla

Proceedings Volume 10149, 1014908 (2017) https://doi.org/10.1117/12.2258028

KEYWORDS: Optical lithography, Etching, Photomasks, Double patterning technology, Extreme ultraviolet, Semiconductors, High volume manufacturing, Metals, Standards development, Lithography, Amorphous silicon, Coating, System on a chip, Materials processing, Silica, Tin

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Proceedings Article | 7 April 2017 Presentation + Paper

Self-aligned blocking integration demonstration for critical sub-40nm pitch Mx level patterning

Angélique Raley, Nihar Mohanty, Xinghua Sun, Richard Farrell, Jeffrey Smith, Akiteru Ko, Andrew Metz, Peter Biolsi, Anton Devilliers

Proceedings Volume 10149, 101490O (2017) https://doi.org/10.1117/12.2257769

KEYWORDS: Optical lithography, Photomasks, Metals, Etching, Double patterning technology, Overlay metrology, Semiconductors, Immersion lithography, Tolerancing, Optical alignment, Dielectrics, System on a chip, Plasma, Plasma etching, Lithography, Back end of line

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Proceedings Article | 4 April 2017 Presentation + Paper

Self-aligned quadruple patterning using spacer on spacer integration optimization for N5

Sophie Thibaut, Angélique Raley, Nihar Mohanty, Subhadeep Kal, Eric Liu, Akiteru Ko, David O'Meara, Kandabara Tapily, Peter Biolsi

Proceedings Volume 10149, 101490I (2017) https://doi.org/10.1117/12.2258173

KEYWORDS: Optical lithography, Double patterning technology, Etching, Error control coding, Semiconductors, Immersion lithography, Chemistry, Error analysis, Semiconducting wafers, Scanning electron microscopy, Line width roughness, Oxides, Spatial frequencies, Atomic layer deposition, Line edge roughness, Plasma

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Proceedings Article | 1 April 2016 Paper

Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications

Angélique Raley, Sophie Thibaut, Nihar Mohanty, Kal Subhadeep, Satoru Nakamura, Akiteru Ko, David O'Meara, Kandabara Tapily, Steve Consiglio, Peter Biolsi

Proceedings Volume 9782, 97820F (2016) https://doi.org/10.1117/12.2219321

KEYWORDS: Titanium dioxide, Etching, Optical lithography, Silicon, Plasma, Silica, Atomic layer deposition, Line width roughness, Semiconducting wafers, Photoresist materials

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Proceedings Article | 24 March 2016 Paper

LER improvement for sub-32nm pitch self-aligned quadruple patterning (SAQP) at back end of line (BEOL)

Nihar Mohanty, Richard Farrell, Cheryl Periera, Kal Subhadeep, Elliott Franke, Jeffrey Smith, Akiteru Ko, Anton DeVilliers, Peter Biolsi, Lei Sun, Genevieve Beique, Erik Hosler, Erik Verdujn, Wenhui Wang, Cathy Labelle, Ryoung-han Kim

Proceedings Volume 9782, 97820Q (2016) https://doi.org/10.1117/12.2219259

KEYWORDS: Etching, Line edge roughness, Optical lithography, Back end of line, Chemistry, Front end of line, Lithography, Ions, Amorphous silicon, Extreme ultraviolet

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Proceedings Article | 19 March 2015 Paper

Fin formation using graphoepitaxy DSA for FinFET device fabrication

Chi-Chun Liu, Fee Li Lie, Vinayak Rastogi, Elliott Franke, Nihar Mohanty, Richard Farrell, Hsinyu Tsai, Kafai Lai, Melih Ozlem, Wooyong Cho, Sung Gon Jung, Jay Strane, Mark Somervell, Sean Burns, Nelson Felix, Michael Guillorn, David Hetzer, Akiteru Ko, Matthew Colburn

Proceedings Volume 9423, 94230S (2015) https://doi.org/10.1117/12.2086053

KEYWORDS: Etching, Lithography, Silicon, Oxides, Atomic layer deposition, Scanning electron microscopy, Polymethylmethacrylate, Image processing, Directed self assembly

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Proceedings Article | 17 March 2015 Paper

Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme

Nihar Mohanty, Elliott Franke, Eric Liu, Angelique Raley, Jeffrey Smith, Richard Farrell, Mingmei Wang, Kiyohito Ito, Sanjana Das, Akiteru Ko, Kaushik Kumar, Alok Ranjan, David O'Meara, Kenjiro Nawa, Steven Scheer, Anton DeVillers, Peter Biolsi

Proceedings Volume 9428, 94280G (2015) https://doi.org/10.1117/12.2085016

KEYWORDS: Etching, Optical lithography, Lithography, Plasma etching, Vacuum ultraviolet, Line edge roughness, Plasma, Semiconducting wafers, Line width roughness, Photomasks

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Proceedings Article | 28 March 2014 Paper

Towards electrical testable SOI devices using Directed Self-Assembly for fin formation

Chi-Chun Liu, Cristina Estrada-Raygoza, Hong He, Michael Cicoria, Vinayak Rastogi, Nihar Mohanty, Hsinyu Tsai, Anthony Schepis, Kafai Lai, Robin Chao, Derrick Liu, Michael Guillorn, Jason Cantone, Sylvie Mignot, Ryoung-Han Kim, Joy Cheng, Melia Tjio, Akiteru Ko, David Hetzer, Mark Somervell, Matthew Colburn

Proceedings Volume 9049, 904909 (2014) https://doi.org/10.1117/12.2046462

KEYWORDS: Etching, Silicon, Polymethylmethacrylate, Semiconducting wafers, Scatterometry, Image processing, 3D modeling, Line edge roughness, Defect detection, Directed self assembly

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Proceedings Article | 28 March 2014 Paper

Dual frequency mid-gap capacitively coupled plasma (m-CCP) for conventional and DSA patterning at 10nm node and beyond

Nihar Mohanty, Akiteru Ko, Christopher Cole, Vinayak Rastogi, Kaushik Kumar, Gerard Schmid, Richard Farrell, Todd Ryan, Erik Hosler, Ji Xu, Moshe Preil

Proceedings Volume 9054, 90540R (2014) https://doi.org/10.1117/12.2048320

KEYWORDS: Etching, Optical lithography, Plasma, Semiconducting wafers, Double patterning technology, Lithography, Photons, Back end of line, Metals, Directed self assembly

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Proceedings Article | 27 March 2014 Paper

Manufacturability considerations for DSA

Richard Farrell, Erik Hosler, Gerard Schmid, Ji Xu, Moshe Preil, Vinayak Rastogi, Nihar Mohanty, Kaushik Kumar, Michael Cicoria, David Hetzer, Anton DeVilliers

Proceedings Volume 9051, 90510Z (2014) https://doi.org/10.1117/12.2048396

KEYWORDS: Polymethylmethacrylate, Optical lithography, Photoresist materials, Line edge roughness, Etching, Line width roughness, Picosecond phenomena, Scanning electron microscopy, Annealing, Directed self assembly

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Proceedings Article | 26 March 2013 Paper

Fabrication of 28nm pitch Si fins with DSA lithography

Gerard Schmid, Richard Farrell, Ji Xu, Chanro Park, Moshe Preil, Vidhya Chakrapani, Nihar Mohanty, Akiteru Ko, Michael Cicoria, David Hetzer, Mark Somervell, Benjamen Rathsack

Proceedings Volume 8680, 86801F (2013) https://doi.org/10.1117/12.2011607

KEYWORDS: Optical lithography, Etching, Silicon, Photoresist materials, Finite element methods, Picosecond phenomena, Coating, Polymethylmethacrylate, Lithography, Directed self assembly

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