Dr. Seongbo Shim Profile

Dr. Seongbo Shim

Principal Engineer, Ph.D.

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Publications (14)

Proceedings Article | 10 April 2024 Paper

EUV source pole control for LCDU and CD ellipticity handling in hexagonal contact arrays

Jieun Song, Janghun Kim, Hyung Jong Bae, Sudeok Kim, Soonmok Ha, Woojin Jung, Seokwon Cho, Jeounghun Park, Dohyeon Park, Eunji Lee, Minseung Song, Hyunseung Ha, Giseon Han, Young Joo Choi, Gyeongseok Park, Seongbo Shim, Chan Hwang

Proceedings Volume 12953, 1295309 (2024) https://doi.org/10.1117/12.3010718

KEYWORDS: Mirrors, Metrology, Simulations, Light sources and illumination, Extreme ultraviolet, Source mask optimization, Nanoimprint lithography, Critical dimension metrology, Semiconducting wafers, Phase shifts

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Proceedings Article | 30 March 2017 Paper

Machine learning-based 3D resist model

Seongbo Shim, Suhyeong Choi, Youngsoo Shin

Proceedings Volume 10147, 101471D (2017) https://doi.org/10.1117/12.2257904

KEYWORDS: Lithography, Data modeling, Etching, Metals, Image processing, Resistance, Computer simulations, 3D modeling, Artificial neural networks, Machine learning, Photoresist processing, Standards development, 3D image processing

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Proceedings Article | 23 March 2016 Paper

Etch proximity correction through machine-learning-driven etch bias model

Seongbo Shim, Youngsoo Shin

Proceedings Volume 9782, 97820O (2016) https://doi.org/10.1117/12.2219057

KEYWORDS: Optical lithography, Etching, Artificial neural networks, Neural networks, Machine learning, Optical proximity correction, Critical dimension metrology, Geometrical optics

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Proceedings Article | 15 March 2016 Paper

Machine learning (ML)-guided OPC using basis functions of polar Fourier transform

Suhyeong Choi, Seongbo Shim, Youngsoo Shin

Proceedings Volume 9780, 97800H (2016) https://doi.org/10.1117/12.2219073

KEYWORDS: Metals, Raster graphics, Bessel functions

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Proceedings Article | 19 March 2015 Paper

Verification of directed self-assembly (DSA) guide patterns through machine learning

Seongbo Shim, Sibo Cai, Jaewon Yang, Seunghune Yang, Byungil Choi, Youngsoo Shin

Proceedings Volume 9423, 94231E (2015) https://doi.org/10.1117/12.2085644

KEYWORDS: Lithography, Optical lithography, Polymers, Photomasks, Machine learning, Directed self assembly, Optical proximity correction, Electrical engineering, Global Positioning System, 193nm lithography

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Proceedings Article | 28 March 2014 Paper

Synthesis of lithography test patterns through topology-oriented pattern extraction and classification

Seongbo Shim, Woohyun Chung, Youngsoo Shin

Proceedings Volume 9053, 905305 (2014) https://doi.org/10.1117/12.2046142

KEYWORDS: Semiconductors, Lithography, Metals, Fourier transforms, Image classification, Double patterning technology, Raster graphics, Electrical engineering, Vector spaces, Tolerancing

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Proceedings Article | 12 April 2013 Paper

The effect of mask and source complexity on source mask optimization

Seung-Hune Yang, Ningning Jia, SeongBo Shim, Dmitry Vengertsev, Jungdal Choi, Ho-Kyu Kang, Young-Chang Kim

Proceedings Volume 8683, 86830C (2013) https://doi.org/10.1117/12.2011993

KEYWORDS: Lithography, Electron beams, Error analysis, Monte Carlo methods, Photomasks, Source mask optimization, Optical proximity correction, Critical dimension metrology, Neodymium, Semiconducting wafers

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Proceedings Article | 8 November 2012 Paper

The new test pattern selection method for OPC model calibration, based on the process of clustering in a hybrid space

Dmitry Vengertsev, Kihyun Kim, Seung-Hune Yang, Seongbo Shim, Seongho Moon, Artem Shamsuarov, Sooryong Lee, Seong-Woon Choi, Jungdal Choi, Ho-Kyu Kang

Proceedings Volume 8522, 85221A (2012) https://doi.org/10.1117/12.953827

KEYWORDS: Lithography, Principal component analysis, Data modeling, Calibration, Logic devices, Optical proximity correction, Semiconducting wafers, Optics manufacturing, Statistical modeling, Model-based design

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Proceedings Article | 5 April 2011 Paper

Physical simulation for verification and OPC on full chip level

Seongbo Shim, Seongho Moon, Youngchang Kim, Seongwoon Choi, Younghee Kim, Bernd Küchler, Ulrich Klostermann, Munhoe Do, Sooryoung Lee

Proceedings Volume 7973, 79732I (2011) https://doi.org/10.1117/12.879577

KEYWORDS: Lithography, Data modeling, Calibration, Computer simulations, Image quality, Signal processing, Photomasks, Optical proximity correction, Nanoimprint lithography, System on a chip

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Proceedings Article | 5 April 2011 Paper

The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate

Jeong-Geun Park, Sang-wook Kim, Seong-Bo Shim, Sung-Soo Suh, Hye-Keun Oh

Proceedings Volume 7974, 79740Y (2011) https://doi.org/10.1117/12.881472

KEYWORDS: Calibration, Etching, Control systems, Scanning electron microscopy, Photomasks, Transistors, Critical dimension metrology, Performance modeling, Personal protective equipment, Instrument modeling

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Proceedings Article | 23 March 2011 Paper

Investigating the performance of directional boundary layer model through staged modeling method

Moon-Gyu Jeong, Won-Chan Lee, Seung-Hune Yang, Sung-Hoon Jang, Seong-Bo Shim, Young-Chang Kim, Chun-Suk Suh, Seong-Woon Choi, Young-Hee Kim

Proceedings Volume 7973, 79732F (2011) https://doi.org/10.1117/12.879604

KEYWORDS: Cadmium, Data modeling, Error analysis, Photomasks, Artificial intelligence, Optical proximity correction, Neodymium, Semiconducting wafers, Statistical modeling, Performance modeling

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Generally speaking, the models used in the optical proximity effect correction (OPC) can be divided into three parts, mask part, optic part, and resist part. For the excellent quality of the OPC model, each part has to be described by the first principles. However, OPC model can't take the all of the principles since it should cover the full chip level calculation during the correction. Moreover, the calculation has to be done iteratively during the correction until the cost function we want to minimize converges. Normally the optic part in OPC model is described with the sum of coherent system (SOCS[1]) method. Thanks to this method we can calculate the aerial image so fast without the significant loss of accuracy. As for the resist part, the first principle is too complex to implement in detail, so it is normally expressed in a simple way, such as the approximation of the first principles, and the linear combinations of factors which is highly correlated with the chemistries in the resist. The quality of this kind of the resist model depends on how well we train the model through fitting to the empirical data. The most popular way of making the mask function is based on the Kirchhoff's thin mask approximation. This method works well when the feature size on the mask is sufficiently large, but as the line width of the semiconductor circuit becomes smaller, this method causes significant error due to the mask topography effect. To consider the mask topography effect accurately, we have to use rigorous methods of calculating the mask function, such as finite difference time domain (FDTD[2]) and rigorous coupled-wave analysis (RCWA[3]). But these methods are too time-consuming to be used as a part of the OPC model. Until now many alternatives have been suggested as the efficient way of considering the mask topography effect. Among them we focused on the boundary layer model (BLM) in this paper. We mainly investigated the way of optimization of the parameters for the BLM since the feasibility of the BLM has been investigated in many papers[4][5][6]. Instead of fitting the parameters to the wafer critical dimensions (CD) directly, we tried to use the aerial image (AI) from the rigorous simulator with the electromagnetic field (EMF) solver. Usually that kind of method is known as the staged modeling method. To see the advantages of this method we conducted several experiments and observed the results comparing the method of fitting to the wafer CD directly. Through the tests we could observe some remarkable results and confirmed that the staged modeling had better performance in many ways.

Proceedings Article | 11 December 2009 Paper

Development and evaluation of new MRC parameter for aggressive mask optimization

Seong-bo Shim, Young-chang Kim, Seong-hoon Jang, Hee-bom Kim, Sung-woo Lee, Seong-woon Choi, Han-ku Cho, Chan-hoon Park

Proceedings Volume 7520, 75200U (2009) https://doi.org/10.1117/12.839398

KEYWORDS: Manufacturing, Inspection, Scanning electron microscopy, Image quality, Photomasks, Source mask optimization, SRAF, Critical dimension metrology, Tolerancing, Defect inspection

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Proceedings Article | 4 December 2008 Paper

Optimization of mask manufacturing rule check constraint for model based assist feature generation

Seongbo Shim, Young-chang Kim, Yong-jin Chun, Seong-Woo Lee, Suk-joo Lee, Seong-woon Choi, Woo-sung Han, Seong-hoon Chang, Seok-chan Yoon, Hee-bom Kim, Won-tai Ki, Sang-gyun Woo, Han-gu Cho

Proceedings Volume 7140, 714030 (2008) https://doi.org/10.1117/12.804668

KEYWORDS: Lithography, Manufacturing, Image quality, Photomasks, Optical proximity correction, SRAF, Critical dimension metrology, Optimization (mathematics), Semiconducting wafers, Tolerancing

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SRAF (sub-resolution assist feature) generation technology has been a popular resolution enhancement technique in photo-lithography past sub-65nm node. It helps to increase the process window, and these are some times called ILT(inverse lithography technology). Also, many studies have been presented on how to determine the best positions of SRAFs, and optimize its size. According to these reports, the generation of SRAF can be formulated as a constrained optimization problem. The constraints are the side lobe suppression and allowable minimum feature size or MRC (mask manufacturing rule check). As we know, bigger SRAF gives better contribution to main feature but susceptible to SRAF side lobe issue. Thus, we finally have no choice but to trade-off the advantages of the ideally optimized mask that contains very complicated SRAF patterns to the layout that has been MRC imposed applied to it. The above dilemma can be resolved by simultaneously using lower dose (high threshold) and cleaning up by smaller MRC. This solution makes the room between threshold (side lobe limitation) and MRC constraint (minimum feature limitation) wider. In order to use smaller MRC restriction without considering the mask writing and inspection issue, it is also appropriate to identify the exact mask writing limitation and find the smart mask constraints that well reflect the mask manufacturability and the e-beam lithography characteristics. In this article, we discuss two main topics on mask optimizations with SRAF. The first topic is on the experimental work to find what behavior of the mask writing ability is in term of several MRC parameters, and we propose more effective MRC constraint for aggressive generation of SRAF. The next topic is on finding the optimum MRC condition in practical case, 3X nm node DRAM contact layer. In fact, it is not easy to encompass the mask writing capability for very complicate real SRAF pattern by using the current MRC constraint based on the only width and space restriction. The test mask for this experimental work includes not only typical split patterns but also real device patterns that are generated by in-house model-based assist feature generation tool. We analyzed the mask writing result for typical patterns and compared the simulation result, and wafer result for real device patterns.

Proceedings Article | 11 April 2008 Paper

Study of the mask topography effect on the OPC modeling of hole patterns

Seong-bo Shim, Young-chang Kim, Suk-joo Lee, Seong-woon Choi, Woo-sung Han

Proceedings Volume 6924, 69243R (2008) https://doi.org/10.1117/12.774025

KEYWORDS: Lithography, Apodization, Finite-difference time-domain method, Optical lithography, Data modeling, 3D modeling, Photomasks, Optical simulations, Optical proximity correction, Virtual reality

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