This PDF file contains the front matter associated with SPIE Proceedings Volume 12056, including the Title Page, Copyright information, Table of Contents, and Conference Committee listings.

Selective etching of several hard-to-etch materials is achieved by cyclic repetition of conversion into volatile organometallics followed by volatilization. A feature of this etching technology is the processes of adding volatility to these materials by converting the surface of the materials into intermediatory generated organometallics with thermal stability; one key point is stabilizing materials for the organometallics, and the other is a reaction pathway via inherently stable organometallics. In layers of Co metal, one hard-to-etch material, a specific oxidation state of Co in the Co oxidizing first step avoids the reaction pathways that generate a mixture of multiple organo-cobalt complexes in the following step. For La2O3, another hard-to-etch material, an organo-lanthanum complex generated in the ligand adsorbing first step is immediately stabilized by a stabilizer. The surface-modified layer composed of the resultant stabilized organo-lanthanum complex prevents the ligand species from diffusing deeply and from increasing the modified layer thickness. The following step, in both cases, is rapid thermal annealing by infrared (IR) irradiation to remove the surface modified layer without decomposition. The etched amount increases as the number of cycle repetitions increases with high selectivity.

Through‐silicon via etch (TSV) is critical to current and future advanced packaging schemes. For heterogeneous integration approaches in particular, where modular components are tightly packed together, these processes play an integral role. While etch processes for silicon appear well understood and the frontiers of plasma etch have led us to advanced cyclic processes for device fabrication such as atomic layer etching, TSV applications are fundamentally different due to their relative size and aspect ratio targets. Unlike small-scale etching, TSV feature etching has not shown exponential change over time. To achieve TSV targets such as high etch rate, high aspect ratio, and clean profiles to support filling, known solutions are employed such as cryogenic wafer temperatures, alternative hard mask schemes, and extremely short gas cycle times; these solutions require specialized equipment and/or a more complex integration scheme. We explore the creation of high-aspect ratio, diffusion-limited TSV etches with high PR selectivity (<50:1) and high aspect ratios while simultaneously aiming for a high etch rate all while using non-cryogenic temperatures and a standard photoresist mask. A focus on sidewall profile and sidewall damage is maintained.

In this work, we present two different approaches to pattern Ru metal lines at a metal pitch of 18 nm, by making use of self-aligned double patterning (SADP) in combination with EUV lithography. The first and more conventional patterning approach is to define the 18 nm pitch gratings into a hard mask by means of SADP, which is consequently transferred into the Ru layer by means of direct metal etch. The second and more innovative approach consists of a combination of direct metal etch and damascene filling of Ru. This so-called mixed flow is a patterning-friendly approach which enables the integration of self-aligned cuts and vias. We will share the schematics as well as the results for 18 nm pitch Ru gratings on 300 mm Si wafers for both approaches. Finally, we will discuss and demonstrate the enablement of selfaligned cuts and vias for the mixed flow, which makes this patterning flow a promising alternative to standard damascene patterning for future interconnects at sub-20 nm metal pitches.

As technology nodes continue to scale down, maintaining roughness and defectivity during the pattern transfer becomes more challenging. For the smallest features, Metal-Organic Resists (MOR) are preferred due to their better selectivity than Chemically Amplified Resists (CAR). However, MORs are usually negative tone resists. Primarily based on defectivity reasons, dark field Extreme Ultraviolet (EUV) masks are strongly preferred over light field EUV masks. Therefore, the MOR resist is more suited for pillar patterning than hole patterning. The purpose of this paper is to show that exposing pillars with MOR and converting them into holes can yield better roughness and defectivity than patterning holes with CAR directly. A similar comparison is done for the tone reversal of lines and spaces. It is shown that the Local Critical Dimension Uniformity (LCDU) of holes and the Line Edge Roughness (LER) of lines/spaces are well conserved throughout the tone inversion process.

Selective plasma etching among different dielectric materials is crucial to the manufacturing of advanced logic and memory devices. For instance, in self-aligned contact (SAC) etching, achieving highly selective SiO₂ etching over Si₃N₄ is essential. By contrast, in self-aligned multi-patterning (SAMP), selective Si₃N₄ spacer removal over SiO₂ and Si is necessary. To effectively control the relative etch rates of various dielectric materials, etch gas chemistry optimization [for instance, see J. Vac. Sci. Technol. A 36, 040601 (2018), J. Vac. Sci. Technol. A 34, 041307 (2016)., J. Vac. Sci. Technol. A 35, 01A102 (2017), etc.] has been extensively investigated. On the other hand, hardware capabilities such as direct current superposition (DCS) and must also be considered for their effects on plasma physics and plasma-surface interactions. In this study, we examine the etch behavior for various dielectric materials e.g. SiO₂, Si3N₄, and low-k dielectrics in a TEL dual-frequency CCP chamber. Specifically, we focus on the gas ratio and DCS effects in a CF₄/H₂/Ar plasma. Contrary to the monotonically decreasing etch rates for SiO₂ and low-k vs. increasing H₂/CF₄ flow ratio in accordance with decreasing F/CF_x density ratio, the experimental blanket Si₃N₄ etch rate exhibits a local maximum at H₂/(CF₄+H₂) = 15%. Chamber-scale plasma simulations using the Hybrid Plasma Equipment Model (HPEM) indicate that the HF density is peaked at almost the same gas ratio. In addition, atomistic molecular dynamics (MD) and density functional theory (DFT) simulations reveal hydrogen’s role in modifying the Si₃N₄ surface through N-H bond formation, thereby creating a hydrophilic surface on which HF adsorption is enhanced. Finally, computed reactant flux trends also demonstrate that the effect of DC superposition (DCS) on the relative orders of various ion and neutral reactant fluxes to the wafer is significantly weaker compared to that of the H₂/(CF₄+H₂) flow ratio. This suggests that the application of DCS aimed at differential charging mitigation is not expected to induce major changes in inherent material etch selectivity. These fundamental learnings provide insights to guide process development and optimization for common dielectric etch applications.

This paper demonstrates a full-chip OPC correction flow based on deep-learning etch model in a DUV litho-etch case. The flow leverages SEM metrology (eP5 fast E-beam tool, ASML-HMI) to collect massive data, automated metrology software (MXP, ASML-Brion) to extract high quality gauges, and deep-learning etch modeling (Newron etch, ASML-Brion) to capture complicated etch behaviors. The model calibration and verification are performed using a combined data from a test and real chip wafer to ensure sufficient pattern coverage. The model performance of Newron etch is benchmarked against a term-based etch model, wherein Newron etch model shows significant accuracy improvement in the model calibration (<50% for test patterns and <35% for real chip pattern). The Newron etch model is proven stable with a comparable performance in the model verification. Particularly, strong loading effects from underlying sublayer are observed in the full chip wafer, and effectively captured by the Newron etch with a sublayer-aware model form. The calibrated Newron etch model is successfully applied in a model-based etch OPC tape-out with new mask design rules but the same litho-etch process conditions. Compared to the term-based model, Newron etch also shows significant accuracy improvement.

The development of new technologies and advanced nodes is capitally intensive due to process design strategies that involve dependent unit processes with different yields and performances. This has led to the exploration of model-based optimization to cut the cost and time of recipe creation; however, computational optimization of semiconductor processes is quite challenging due to multi-dimensional parameter spaces and limited experimental data. SandBox Studio™ AI is a computational tool that automatically builds a hybrid physics-based and machine learning model that can be used to predict optimal process recipes and explore novel process changes such as different incoming mask geometries and step durations. Herein, we show the utilization of SandBox Studio™ AI to build a computational representation of a cyclic etch and deposition process of a high aspect ratio channel etch with the following detrimental effects – bowing, resist over-etching, clogging via deposition, and twisting. The model was calibrated to a synthetic data set of thirteen experiments with five varying process parameters. Then, an optimal recipe was predicted that minimized the observed detrimental effects. The model was then used to explore different incoming mask geometries and step durations to improve the recipe even further. This capability is made possible by the software’s foundational physics-based model and is not possible using conventional statistics and machine learning based tools.

Switching of phase change memory (PCM) materials between crystalline and amorphous phase with electrical pulses and optical properties make it an important candidate for storage class memory and neuromorphic computing. However, PCM materials can be sensitive to air exposure during integration, therefore in-vacuo RIE and encapsulation is important to provide the required oxygen diffusion barrier. Low temperature SiN deposition can be used for low thermal budget integration schemes provided a good film conformality is achieved and damage or etching to the PCM elements is mitigated. In this work, ammonia- (NH3-) free, plasma enhanced chemical vapor deposition (PECVD) SiN films deposited at 40°C (microwave plasma) and 200°C (inductively coupled plasma), are compared and wet etch rates and optical properties are evaluated. NH3-free SiN films were deposited using SiH4, N2, H2, and Ar as source gases. Tuning the plasma parameters during encapsulation we observed simultaneous selective etching of GST and controlled SiN film deposition. Hydrogen and argon addition to the plasma mixture provided the main control knob for in-situ GST trimming during deposition, avoiding any type of elemental or structural damage to the GST films.

In this talk we present core technology solutions for EUV Patterning and co-optimization between EUV resist and underlayer coating, development and plasma etch transfer to achieve best in class patterning performance. We will introduce new hardware and process innovations to address EUV stochastic issues, and present strategies that can extend into High NA EUV patterning. A strong focus will be placed on dose reduction opportunities, thin resist enablement and resist pattern collapse mitigation technologies. CAR and MOR performance for leading edge design rules will be showcased. As the first High NA EUV scanner is scheduled to be operational in 2023 in the joint high NA lab in Veldhoven, Tokyo Electron will collaborate closely with imec, ASML and our materials partners to accelerate High NA learning and support EUV roadmap extension.

As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.

Buried power rail (BPR), a novel integration approach for further device scaling, brings in new patterning needs and requirements, the most importantly, the challenging middle-of-line (MOL) patterning process steps. In this paper, some of the critical plasma dry etch development processing results for the FinFET device flow with BPR integrated are presented. Mainly, the study was focused on plasma dry etch development of high aspect ratio Via contact to BPR metal (VBPR) and Trench contact etch (M0A) to the source/drain (S/D) device region. We demonstrate the short-free M0A (no attack on the neighboring gates) contact etch to the S/D, with the high etch selectivity values obtained in case of the dielectric SiO2 trench etch to the thin Si3N4 liner (deposited over epitaxial S/D), and subsequently the high selectivity values during SiN liner etch to the underlying S/D (SiN liner etch results in 0nm epitaxial film loss). Patterning of high aspect ratio (HAR) Via consisting of the multi-stack, SiO2/SiN/SiO2/SiN dielectric, landing on the bottom BPR metal was achieved, with the target critical dimension (CD) required to avoid shorting to the adjacent gates. Additionally, we report our learnings on how choice of buried power metal (W, Ru and Mo) impacts the etch requirements, i.e., the etch challenges associated by using Ru and Mo as a replacement for standardly used W metal.

In order to fully utilize the potential of the latest and greatest scanner overlay performance capability in a manufacturing environment, all other (process-induced) overlay contributors should be well understood and eliminated where possible. While overlay penalties that slowly vary across the wafer and/or within each exposure field can easily be corrected with the available scanner correction knobs, this is less likely going to happen for overlay signatures that manifest themselves on a much shorter length scale. We refer to length scales that are comparable to the floorplan of the integrated circuit itself. A deep understanding of these process induced overlay contributions is required to take away their root causes. Several non-scanner overlay contributors are known that may have an impact on the scanner exposure field overlay performance. Of course, the quality of the mask itself plays an important role. Mask writing errors correlate one-to-one with the on-wafer overlay performance. Local stress effects may contribute to the intra-die overlay performance too. We extensively addressed the layer stress impact on the intra-field overlay in an earlier publication. In that work, an interesting observation was made. The etch-induced overlay contribution turned out to be largely independent of the layer stress in which the pattern was etched. The conclusion was drawn that the etch-induced overlay penalties can be optimized separately from layer stress related overlay effects. In this work, the focus will be on the etch-induced overlay penalties only. We addressed the etch-induced overlay impact already before. Surprisingly, the etch-induced overlay penalties showed up in every exposure field despite the fact that the etch tool itself is not exposure field aware. For the use-case we investigated, the magnitude of the etch-induced intra-field overlay penalty was around 1-nm. This comes close to the scanner baseline overlay performance. A relation was found with the pattern density distribution and a dependency with the etch tool settings was observed. We identified the Spin-On-Glass and/or Spin-On-Carbon (Hard Mask) etch as the potential root cause. A hypothesis was proposed that was in line with the experimental observations. In this experimental work, we have continued the investigation by validating the hypothesis proposed earlier. Since the hypothesis was based on the pattern density distribution within the exposure field in combination with the deflection of ions due to surface charging effects, both the mask and the etch tool recipe settings per layer have been changed. We show that the etch-induced intra-field overlay penalties can indeed be controlled by changing the etch tool recipe settings per layer. However, the underlying mechanism turned out to be different from what we expected. In the current paper, we will present a new concept that much better explains all the experimental results we have obtained so far. Based on this new understanding, we experimentally demonstrate that etch-induced intra-field overlay penalties can be mitigated by optimizing the etch tool recipe settings.

Identification of optimal recipes for multi-step and cyclic etch processes where the outcome of each step depends on the progression of the previous steps is a major challenge. Selecting the order and duration of each step is typically performed by a tedious trial and error process where the number of experimental trials scales exponentially with process complexity. Here we present a simulation-based methodology that significantly accelerates the process. We use limited experimental data taken at various process conditions, which may include pressure, gas type, gas flow rate, power, bias, and time to calibrate a step-aware reduced-order physics-based etch and deposition model. This model is used to generate predictions with steps permuted in any desired order and duration. The calibrated model predicts ordering, timing, and possible cycling of each step to achieve desired etch targets. The methodology is demonstrated on a multilayer stack with three possible steps, including etch and deposition. It is shown that the total number of experiments required for the proposed methodology is significantly less than that required by standard methods like full-factorial design of experiment. We also demonstrate how the etch data and the resulting calibrated model can be used to determine the optimal etch recipe for different aperture and/or mask geometries without having to perform further experiments.

Extreme ultraviolet (EUV) lithography has been used for mass production for several years. Now the resolution limit of current 0.33 NA single exposure has been approaching. To enhance the resolution limit, high NA exposure tool has been developing. At the limit, not only the stochastic failures1, but also patterning trade-off has been becoming challenging. In this paper, to overcome the patterning trade-off of LS and CH, several approaches were demonstrated for both CAR and MOR. As for chemically amplified resist (CAR), to overcome the patterning trade-off of line and space, two different approaches were demonstrated. One was a developer rinse process optimization, and the other was a top deposition treatment during etching process. By using the two approaches, pitch 24 nm LS patterns were successfully transferred. As to CAR CH patterning, a new shrink technique during etch process was successfully tested for sub 15 nm hole patterning. No missing hole detected at 12 nm hole size by voltage contrast metrology. For tighter nodes, spin-on metal oxide resist (MOR) have been considering to be used because it offers a series of advantages. It has high sensitivity and resolution because of its high photon absorption and simple reaction mechanism. It also inherently has a higher etch resistance which enables resist thickness thinner and collapse margin higher. Spin-on process of MOR is expect to contribute high productivity which is essential for high volume manufacturing (HVM). Because defect reduction is one of the key points to enable MOR process for HVM, continuous investigation of defect mitigation has been done. For pitch 32 nm LS, the mitigation was confirmed by fine optimization with the combination of the etch process and the implementation of new under layers. As to pitch 28nm line and space, optimized illumination gave better defect process windows. Moreover, a new wet developer process was successfully proposed to prevent pitch 36 nm hexagonal pillars collapse during wet development with 25% higher EUV sensitivity.